RESOURCES
Glossary
Key terms and definitions used across the Q-PLANET pilot line and technologies.
A design kit for packaging and assembly: rules, templates, models, and constraints that help ensure a chip can be packaged, fiber-coupled, wire-bonded, mounted, and tested.
The process of putting fabricated chips and subcomponents together into a functional unit.
Post-fabrication packaging steps after the chip has been made.
Post-wafer steps: dicing, assembly, bonding, fiber attach, packaging, inspection, testing.
Joining materials or connecting chips, wires, or wafers.
Designing the chip and package together.
Packaging photonic and electronic chips close together.
The tools, documentation, PDKs, ADKs, examples, and workflows that make a fabrication technology usable by designers.
Designing a component so it can be fabricated reliably.
Designing a chip layout so that it can be assembled, connected, fiber-coupled, thermally managed, and tested.
Geometrical and process constraints that designers must respect: minimum line width, spacing, bend radius, pad size, fiber pitch, etc.
An individual chip cut from a wafer.
Positioning a chip die on a package, carrier, or substrate.
Coupling light through the side/facet of a chip.
A partner or customer who uses the produced component in an application.
Permanently aligning and fixing optical fibers to a photonic chip.
A facility that fabricates chips for users or designers.
A mid-term partnership framework under which SGAs are implemented.
Wafer fabrication steps that create the chip structures.
A patterned structure that couples light vertically between a fiber and a chip.
Integrating different materials directly in one process or on one substrate.
Combining separately fabricated chips or components into one assembly.
A scale describing manufacturing maturity.
A wafer shared by several designs or users, reducing cost.
A pilot line accessible beyond the core consortium, often to SMEs, startups, and researchers.
The side surface of a chip where light exits or enters.
The process of enclosing, mounting, connecting, protecting, and interfacing a chip so it can be used in a system.
A set of design files, verified building blocks, layout rules, simulation models, and documentation that lets users design chips compatible with a foundry’s fabrication process.
A chip containing optical components such as waveguides, couplers, filters, modulators, cavities, splitters, and sometimes lasers or detectors.
A pre-industrial manufacturing line used to validate processes before full-scale production.
The ordered sequence of fabrication steps: deposition, lithography, etching, bonding, inspection, etc.
A pilot line with enough industrial structure to fabricate, assemble, test, and deliver components repeatedly.
A low-loss, CMOS-compatible dielectric photonic material transparent over a broad range, including much of the visible and near-IR.
Integrated photonics based mainly on silicon.
A silicon layer on an insulating oxide layer, widely used in silicon photonics.
Cutting a wafer into individual dies.
Glass-like insulating material often used as cladding for waveguides.
A grant agreement under a broader framework partnership.
A waveguide structure that expands or adapts the optical mode.
The moment in the schedule where the chip design is considered finalized and is sent to the foundry / fab for fabrication. Any change to optical / electrical design afterwards becomes expensive or impossible.
Controlling heat generation and temperature stability.
A scale from 1 to 9 describing technology maturity. TRL4 is lab validation; TRL6 is prototype demonstration in relevant environment; TRL8 is qualified system.
A flat disk of semiconductor or glass material on which many chips are fabricated together.
Making electrical connections with fine wires between chip pads and a package or PCB.